Use of high-level design information for enabling automation of fine-grained power gating

Leakage power reduction through power gating requires considerable design and verification effort. Conventionally, extensive analysis is required for dividing a heterogeneous design into power domains and generating control signals for power switches because of the need to preserve design behavior. In this thesis, I present a scheme which uses high-level design description to automatically generate a collection of finegrain power domains and associated control signals. For this purpose, we explore the field of high-level design languages and select rule-based languages on Quality-ofResult metrics. We provide algorithms to enable automatic power domain partitioning in designs generated using rule-based languages. We also describe techniques for collecting the dynamic activity characteristics of a domain, viz. total inactivity and frequency of inactive-active transitions. These metrics are necessary to decide the generated domains' viability for power gating after accounting for energy loss due to transitions. Our automated power gating technique provides power savings without exacerbating the verification problem because the power domains are correct by construction. We illustrate our technique using various test-cases: two wireless decoder designs, a million-point sparse FFT design and a RISC processor design. Thesis Supervisor: Arvind Title: Johnson Professor of Computer Science and Engineering